1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly relates to improvement in data retention characteristics of a semiconductor memory device storing data in a capacitor. More particularly, the present invention relates to a semiconductor memory device, in which data of one bit is stored by memory cells of two bits. More specifically, the present invention relates to a configuration for ensuring reliability of gate insulating films of memory cells in an embedded memory integrated with a logic on the same semiconductor substrate, without impairing the data retention characteristics.
2. Description of the Background Art
In the field of data processing and others, a circuit device called a system LSI (large scale integrated circuit) having a logic such as a processor and a memory device integrated in a common semiconductor chip has been widely used in order to process data at high speed with low power consumption.
In such system LSI, the configuration in which the logic and the memory device are interconnected through on-chip interconnection lines provides the following advantages: (1) due to smaller load of signal interconnection lines than that of the on-board wires, data/signals can be transmitted at high speed; (2) due to no restriction on the number of pin terminals, the number of data bits can be increased, and the band width of data transfer can be widened; (3) due to integration of a plurality of components on a common semiconductor chip, the size of the system can be reduced compared to the configuration where discrete components are arranged on a board, and thus, a small sized, light-weight system is implemented; and (4) macros prepared as a library can be arranged as the components formed on the semiconductor chip, and thus, design efficiency is improved.
By virtue of the advantages described above, the system LSI has been widely used in various fields. DRAM (dynamic random access memory), SRAM (static random access memory), non-volatile semiconductor memory device and other memory devices have been used for the memory device to be integrated. For the logic to be merged, a processor performing control and processing, an analog processing circuit such as an A/D converter, a logic circuit performing a specialized logical operation and others have been employed.
When integrating a processor and a memory device in the LSI system, it is desired to form the logic and the memory device in the same manufacturing steps as many as possible for the purposes of reducing the number of manufacturing steps and cost. A DRAM stores data in a capacitor in the form of charges. This capacitor has electrodes called a storage node electrode and a cell plate electrode formed above a semiconductor substrate region. Such a memory capacitor is generally called a stacked capacitor, and has a complicated shape like a hollow cylinder to achieve a large capacitance value with a small occupying area.
Thus, in the DRAM-logic hybrid process of forming the DRAM and the logic in the same manufacturing process, even if the transistor of the logic and the transistor of the DRAM are formed in the same manufacturing process, additional manufacturing steps of forming the capacitor of the DRAM, and a planarization process for alleviating unevenness or steps between the DRAM and the logic and between the DRAM memory array and the peripheral portion, due to the three dimensional structure of the capacitor of the DRAM, become necessary. This significantly increases the number of manufacturing steps and also increases the chip cost.
In an SRAM, a memory cell is formed of four transistors and two load elements. Normally, the load elements are formed with MOS transistors (insulated gate type field effect transistors), and capacitors or the like are not used. Accordingly, an SRAM can be formed by a full CMOS logic process, and hence, the SRAM and the logic can be formed in the same manufacturing process.
The SRAM, due to its high speed operability, is conventionally used as a cache memory for a processor, a register file memory or the like.
Further, the SRAM has a memory cell formed of a flip-flop circuit, and data is retained as long as a power supply voltage is supplied. Thus, unlike the DRAM, the SRAM does not require refreshing for retention of data, and complicated memory control associated with the refreshing, indispensable to the DRAM, is unnecessary for the SRAM. Thus, the SRAM, simpler in control than the DRAM, has been widely used as a main memory of a portable information terminal or the like, to simplify the system configuration.
However, a portable information terminal now requires a memory of even larger storage capacity, as it is required to handle a large amount of data such as audio and image data, as its recent progress in functionality.
In the DRAM, the memory cell is shrunk along with the progress of a miniaturization process. For example, a cell size of 0.3 xcexcm2 has been implemented according to the 0.18 xcexcm DRAM process. In contrast, in the SRAM, a full CMOS memory cell consists of six MOS transistors in total with two P channel MOS transistors and four N channel MOS transistors. Therefore, even if the miniaturization process advances, it is necessary to isolate an N well for forming P channel MOS transistors from a P well for forming N channel MOS transistors in a memory cell. The constraints of such an inter-well isolation distance hinder shrinkage of the memory size of the SRAM, compared to the DRAM. For example, in the 0.18 xcexcm CMOS logic process, the memory size of the SRAM is 7 xcexcm2 or so, which is more than 20 times the memory size of the DRAM. Accordingly, if the SRAM is utilized as a main memory of large storage capacity, the chip size will significantly increase. It would be extremely difficult to merge an SRAM of storage capacity of 4 Mbits or more with a logic within a system LSI of limited chip area.
In view of the foregoing consideration, it can be considered to use a DRAM-based memory for the large capacity embedded memory. Such a DRAM-based embedded memory could be manufactured employing conventional manufacturing processes to some extent, using conventional manufacturing apparatus and steps. With this DRAM-based memory, however, there still arises the above-described problem of step of the capacitor as long as data is stored in the capacitor. It would be impossible to form the DRAM-based memory and the logic through the same manufacturing steps.
In addition, portable terminal equipment is battery-powered, and it is required to reduce current consumption to the greatest possible extent from the standpoint of life time of the battery. Refresh in the data holding mode is performed simply for retention of data. If the current consumption required for this refresh could be reduced, a stand-by current will be reduced, and correspondingly, the life time of battery will increase.
A possible way to reduce current consumption in such refresh may be to decrease the number of times of refreshing, or to lengthen refresh intervals. If data retention characteristics of a memory cell can be improved and data holding time can be lengthened, the refresh interval will be lengthened, and accordingly, the current consumption required for the refresh could be reduced.
As a way of improving the data retention characteristics of the DRAM, a word line driving scheme called a boosted word line scheme has been used conventionally, wherein a selected word line is driven to a voltage level higher than a power supply voltage level in order to transmit data of a full VCC level to memory cells. In this boosted word line scheme, bit lines are driven by a sense amplifier to a power supply voltage level and a ground voltage level upon completion of a sensing operation. Thus, a high voltage corresponding to a difference between the voltage on the selected word line and the ground voltage will be applied between the gate and source of the transistor of a selected memory cell. If such a high voltage is applied between the gate and source of a memory cell transistor, the gate insulating film of the miniaturized transistor will suffer dielectric breakdown.
Particularly in an embedded memory integrated with a logic on the same semiconductor substrate, it is necessary to consider to form the logic transistor and the memory cell transistor in the same manufacturing process. In order to ensure high-speed operability of the logic transistor, the film thickness of the gate insulating film of the logic transistor is made thin. Thus, especially in such a case, dielectric breakdown characteristics of the memory cell transistor will not be ensured.
Another way of improving the data retention characteristics of a memory cell is a word line driving scheme called a negative voltage word line driving scheme, wherein for a memory cell transistor formed of an N channel MOS transistor, a non-selected word line is maintained at a negative voltage level.
In a stand-by state, the memory cell transistor receives a negative voltage at its gate, and a bit line is maintained at an intermediate voltage level, so that a leakage current through the memory cell transistor is suppressed. Accordingly, the data retention characteristics in the stand-by state, or pause refresh characteristics, is improved by this negative voltage word line driving scheme.
When memory cell data is read out according to a selected word line, the bit line voltage is driven to a power supply voltage level or a ground voltage level and latched by a sense amplifier. In this state, out of the memory cells connected to a non-selected word line, or non-selected memory cells, the memory cell connected to a bit line of a ground voltage level has a transistor having a gate receiving a negative voltage, a source attaining a ground voltage level. Thus, the gate to source of such non-selected memory cell attains a reverse-biased state, to prevent the flow of the leakage current from the storage node storing H (logical high) level to the bit line, resulting in increased data retention time of H level data. The operation affecting the charges stored in a non-selected memory cell at the time of memory cell selection is generally called xe2x80x9cdisturbxe2x80x9d.
In the case of the negative voltage word line driving scheme, the gate to source of a non-selected memory cell transistor is maintained in a reverse-biased state, so that the disturb refresh characteristics is improved. In a non-selected memory cell connected to a bit line at a power supply voltage level, however, a high voltage is applied to its gate insulating film, resulting in degradation of reliability of the gate insulating film, as in the case of the boosted word line scheme described above. Particularly, in data access, duty of a non-selected state of a memory cell is greater than that of a selected state. Thus, in this negative voltage word line driving scheme for suppressing the disturb, the problem of reliability of the gate insulating film becomes more serious.
An object of the present invention is to provide a semiconductor memory device having large storage capacity with a small occupying area, without increasing the number of manufacturing steps.
Another object of the present invention is to provide a semiconductor memory device improved in data retention characteristics without degradation of dielectric breakdown voltage characteristics of memory transistors.
A further object of the present invention is to provide an embedded memory excellent in data retention characteristics and dielectric breakdown voltage characteristics, which can be manufactured in the same manufacturing steps as those for a logic.
The semiconductor memory device according to the present invention includes a plurality of memory sub-blocks each having a plurality of memory cells arranged in rows and columns. The memory sub-block includes a plurality of word lines arranged corresponding to the respective rows and each having memory cells in the corresponding row connected thereto, and a plurality of bit lines arranged corresponding to the respective columns and each having memory cells in the corresponding column connected thereto.
The semiconductor memory device according to the present invention further includes a plurality of sense amplifier bands provided corresponding to the plurality of memory sub-blocks and shared between the adjacent memory sub-blocks. Each sense amplifier band includes a plurality of sense amplifiers provided corresponding to the columns in the corresponding memory sub-blocks and senses and amplifies memory cell data in the corresponding columns when activated. Each sense amplifier receives a first power supply voltage and a second power supply voltage different in a logical level the first power supply voltage as its operating power supply voltages, and performs a sensing operation.
The semiconductor memory device according to the present invention further includes a plurality of bit line isolation circuits arranged corresponding to the sense amplifier bands and the memory sub-blocks. Each bit line isolation circuit includes a plurality of isolation gates each arranged corresponding to the column in the corresponding memory sub-block and connects the sense amplifiers on the corresponding columns to the corresponding bit lines in the corresponding memory sub-block when rendered conductive. Each of the plurality of bit line isolation circuits is formed in a well region different from well regions for the plurality of memory sub-blocks. Each isolation gate is formed of an insulated gate type field effect transistor.
The semiconductor memory device according to the present invention further includes a bit line isolation control circuit which generates an isolation control signal of the first power supply voltage level to a bit line isolation circuit arranged for a selected memory sub-block including a selected memory cell addressed according to a first address signal, and generates a non-selected isolation control signal of a voltage level not smaller in absolute value than the second power supply voltage to a bit line isolation circuit arranged for a memory sub-block sharing the sense amplifiers with the selected memory sub-block.
The semiconductor memory device according to the present invention further includes a word line selection circuit which drives a selected word line on an addressed row in the selected memory sub-block according to a second address signal to the first power supply voltage level, and transmits a voltage higher in absolute value than the second power supply voltage to the word lines other than the selected word line.
By setting the voltage of the bit line isolation gate to the first voltage level of the sense power supply voltage and by connecting the sense amplifier and the bit line, data of the first power supply voltage level latched by the sense amplifier is transmitted to the bit line with threshold voltage loss of the bit line isolation gate caused. Accordingly, the gate to source/drain voltage of the non-selected memory cell transistor can be alleviated by the threshold voltage, so that the dielectric breakdown voltage characteristics of the memory cell transistor is ensured.
Since the selected word line is merely driven to the sense power supply voltage level, the voltage applied between the gate and the source/drain of the selected memory cell transistor can be alleviated. The pause refresh characteristics and the disturb refresh characteristics are both improved, so that the data retention characteristics is improved.
By forming separate well regions for the bit line isolation gates and for the memory cells, it is possible to optimize the well bias of the bit line isolation gate to set the threshold voltage loss as desired. Accordingly, the voltage applied across the gate insulating film of the memory cell transistor can be optimized.
The logic transistor can be utilized as the memory cell transistor, which suppresses an increase of the number of the manufacturing steps.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.